3 μm process

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Semiconductor device fabrication
MOSFET scaling (process nodes)
020 μm – 1968 010 μm – 1971 006 μm – 1974 003 μm – 1977  1.5 μm – 1981 001 μm – 1984 800 nm – 1987 600 nm – 1990 350 nm – 1993 250 nm – 1996 180 nm – 1999 130 nm – 2001 090 nm – 2003 065 nm – 2005 045 nm – 2007 032 nm – 2009 028 nm – 2010 022 nm – 2012 014 nm – 2014 010 nm – 2016 007 nm – 2018 005 nm – 2020 003 nm – 2022
Future 002 nm ~ 2025 001 nm ~ 2027 000.5 nm ~ 2032
Half-nodes Density CMOS Device (multi-gate) Moore's law Transistor count Semiconductor Industry Nanoelectronics
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The 3 μm process (3 micrometer process) is the level of MOSFET semiconductor process technology that was reached around 1977,^[1][2] by companies such as Intel.

The 3 μm process refers to the minimum size that could be reliably produced. The smallest transistors and other circuit elements on a chip made with this process were around 3 micrometers wide.

• Intel's 8085, 8086, 8088 CPU's launched in 1976, 1978, 1979, respectively, were manufactured using its 3.2 μm NMOS (HMOS) process.^{[1] [failed verification]}.^{[3][dubious – discuss]}
• Hitachi's 4 kbit HM6147 SRAM memory chip, launched in 1978, introduced the twin-well CMOS process, at 3 μm.^[4]
• Motorola 68000 (MC68000) CPU, launched in 1979, was originally fabricated using an HMOS process with a 3.5 μm feature size.^{[5][circular reference]}
• The ARM1 was launched in 1985 and manufactured on a 3 μm process.^[6]

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